@article {, title = {Direct Determination of Optimal Real-Space Orbitals for Correlated Electronic Structure of Molecules}, journal = {Journal of Chemical Theory and Computation}, volume = {19}, year = {2023}, month = {2023-10}, pages = {7230 - 7241}, abstract = {We demonstrate how to determine numerically nearly exact orthonormal orbitals that are optimal for the evaluation of the energy of arbitrary (correlated) states of atoms and molecules by minimization of the energy Lagrangian. Orbitals are expressed in real space using a multiresolution spectral element basis that is refined adaptively to achieve the user-specified target precision while avoiding the ill-conditioning issues that plague AO basis set expansions traditionally used for correlated models of molecular electronic structure. For light atoms, the orbital solver, in conjunction with a variational electronic structure model [selected Configuration Interaction (CI)] provides energies of comparable precision to a state-of-the-art atomic CI solver. The computed electronic energies of atoms and molecules are significantly more accurate than the counterparts obtained with the orbital sets of the same rank expanded in Gaussian AO bases, and can be determined even when linear dependence issues preclude the use of the AO bases. It is feasible to optimize more than 100 fully correlated numerical orbitals on a single computer node, and significant room exists for additional improvement. These findings suggest that real-space orbital representations might be the preferred alternative to AO representations for high-end models of correlated electronic states of molecules and materials.}, issn = {1549-9618}, doi = {10.1021/acs.jctc.3c00732}, url = {https://pubs.acs.org/doi/10.1021/acs.jctc.3c00732}, author = {Valeev, Edward F. and Harrison, Robert J. and Holmes, Adam A. and Peterson, Charles C. and Penchoff, Deborah A.} } @conference {, title = {O(N) distributed direct factorization of structured dense matrices using runtime systems}, booktitle = {52nd International Conference on Parallel Processing (ICPP 2023)}, year = {2023}, month = {2023-08}, publisher = {ACM}, organization = {ACM}, address = {Salt Lake City, Utah}, isbn = {9798400708435}, doi = {10.1145/3605573.3605606}, url = {https://dl.acm.org/doi/proceedings/10.1145/3605573}, author = {Sameer Deshmukh and Rio Yokota and George Bosilca and Qinxiang Ma} } @inproceedings {, title = {Deep Gaussian process with multitask and transfer learning for performance optimization}, journal = {2022 IEEE High Performance Extreme Computing Conference (HPEC)}, year = {2022}, month = {2022-09}, pages = {1-7}, abstract = {We combine Deep Gaussian Processes with multitask and transfer learning for the performance modeling and optimization of HPC applications. Deep Gaussian processes merge the uncertainty quantification advantage of Gaussian Processes with the predictive power of deep learning. Multitask and transfer learning allow for improved learning efficiency when several similar tasks are to be learned simultaneously and when previous learned models are sought to help in the learning of new tasks, respectively. A comparison with state-of-the-art autotuners shows the advantage of our approach on two application problems.}, doi = {10.1109/HPEC55821.2022.9926396}, author = {Sid-Lakhdar, Wissam M. and Aznaveh, Mohsen and Luszczek, Piotr and Dongarra, Jack} } @conference {, title = {Distributed-Memory Multi-GPU Block-Sparse Tensor Contraction for Electronic Structure}, booktitle = {35th IEEE International Parallel \& Distributed Processing Symposium (IPDPS 2021)}, year = {2021}, month = {2021-05}, publisher = {IEEE}, organization = {IEEE}, address = {Portland, OR}, abstract = {Many domains of scientific simulation (chemistry, condensed matter physics, data science) increasingly eschew dense tensors for block-sparse tensors, sometimes with additional structure (recursive hierarchy, rank sparsity, etc.). Distributed-memory parallel computation with block-sparse tensorial data is paramount to minimize the time-tosolution (e.g., to study dynamical problems or for real-time analysis) and to accommodate problems of realistic size that are too large to fit into the host/device memory of a single node equipped with accelerators. Unfortunately, computation with such irregular data structures is a poor match to the dominant imperative, bulk-synchronous parallel programming model. In this paper, we focus on the critical element of block-sparse tensor algebra, namely binary tensor contraction, and report on an efficient and scalable implementation using the task-focused PaRSEC runtime. High performance of the block-sparse tensor contraction on the Summit supercomputer is demonstrated for synthetic data as well as for real data involved in electronic structure simulations of unprecedented size.}, keywords = {block-sparse matrix multiplication, distributed-memory, Electronic structure, multi-GPU node, parsec, tensor contraction}, url = {https://hal.inria.fr/hal-02970659/document}, author = {Thomas Herault and Yves Robert and George Bosilca and Robert Harrison and Cannada Lewis and Edward Valeev and Jack Dongarra} } @article {, title = {DTE: PaRSEC Enabled Libraries and Applications}, year = {2021}, month = {2021-04}, publisher = {2021 Exascale Computing Project Annual Meeting}, author = {George Bosilca and Thomas Herault and Jack Dongarra} } @article {, title = {{Dynamic DAG scheduling under memory constraints for shared-memory platforms}}, journal = {Int. J. of Networking and Computing}, volume = {11}, number = {1}, year = {2021}, pages = {27-49}, author = {Gabriel Bathie and Loris Marchal and Yves Robert and Samuel Thibault} } @conference {, title = {DeepFreeze: Towards Scalable Asynchronous Checkpointing of Deep Learning Models}, booktitle = {20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGRID)}, year = {2020}, month = {2020-05}, publisher = {IEEE}, organization = {IEEE}, address = {Melbourne, VIC, Australia}, abstract = {In the age of big data, deep learning has emerged as a powerful tool to extract insight and exploit its value, both in industry and scientific applications. One common pattern emerging in such applications is frequent checkpointing of the state of the learning model during training, needed in a variety of scenarios: analysis of intermediate states to explain features and correlations with training data, exploration strategies involving alternative models that share a common ancestor, knowledge transfer, resilience, etc. However, with increasing size of the learning models and popularity of distributed data-parallel training approaches, simple checkpointing techniques used so far face several limitations: low serialization performance, blocking I/O, stragglers due to the fact that only a single process is involved in checkpointing. This paper proposes a checkpointing technique specifically designed to address the aforementioned limitations, introducing efficient asynchronous techniques to hide the overhead of serialization and I/O, and distribute the load over all participating processes. Experiments with two deep learning applications (CANDLE and ResNet) on a pre-Exascale HPC platform (Theta) shows significant improvement over state-of-art, both in terms of checkpointing duration and runtime overhead.}, doi = {https://doi.org/10.1109/CCGrid49817.2020.00-76}, author = {Bogdan Nicolae and Jiali Li and Justin M. Wozniak and George Bosilca and Matthieu Dorier and Franck Cappello} } @conference {, title = {Design and Comparison of Resilient Scheduling Heuristics for Parallel Jobs}, booktitle = {22nd Workshop on Advances in Parallel and Distributed Computational Models (APDCM 2020)}, year = {2020}, month = {2020-05}, publisher = {IEEE Computer Society Press}, organization = {IEEE Computer Society Press}, address = {New Orleans, LA}, author = {Anne Benoit and Valentin Le F{\`e}vre and Padma Raghavan and Yves Robert and Hongyang Sun} } @techreport {, title = {Design, Optimization, and Benchmarking of Dense Linear Algebra Algorithms on AMD GPUs}, journal = {Innovative Computing Laboratory Technical Report}, number = {ICL-UT-20-12}, year = {2020}, month = {2020-08}, publisher = {University of Tennessee}, abstract = {Dense linear algebra (DLA) has historically been in the vanguard of software that must be adapted first to hardware changes. This is because DLA is both critical to the accuracy and performance of so many different types of applications, and because they have proved to be outstanding vehicles for finding and implementing solutions to the problems that novel architectures pose. Therefore, in this paper we investigate the portability of the MAGMA DLA library to the latest AMD GPUs. We use auto tools to convert the CUDA code in MAGMA to the HeterogeneousComputing Interface for Portability (HIP) language. MAGMA provides LAPACK for GPUs and benchmarks for fundamental DLA routines ranging from BLAS to dense factorizations, linear systems and eigen-problem solvers. We port these routines to HIP and quantify currently achievable performance through the MAGMA benchmarks for the main workload algorithms on MI25 and MI50 AMD GPUs. Comparison with performance roofline models and theoretical expectations are used to identify current limitations and directions for future improvements.}, keywords = {AMD GPUs, GPU computing, HIP Runtime, HPC, numerical linear algebra, Portability}, author = {Cade Brown and Ahmad Abdelfattah and Stanimire Tomov and Jack Dongarra} } @conference {, title = {Design, Optimization, and Benchmarking of Dense Linear Algebra Algorithms on AMD GPUs}, booktitle = {2020 IEEE High Performance Extreme Computing Virtual Conference}, year = {2020}, month = {2020-09}, publisher = {IEEE}, organization = {IEEE}, abstract = {Dense linear algebra (DLA) has historically been in the vanguard of software that must be adapted first to hardware changes. This is because DLA is both critical to the accuracy and performance of so many different types of applications, and because they have proved to be outstanding vehicles for finding and implementing solutions to the problems that novel architectures pose. Therefore, in this paper we investigate the portability of the MAGMA DLA library to the latest AMD GPUs. We use auto tools to convert the CUDA code in MAGMA to the HeterogeneousComputing Interface for Portability (HIP) language. MAGMA provides LAPACK for GPUs and benchmarks for fundamental DLA routines ranging from BLAS to dense factorizations, linear systems and eigen-problem solvers. We port these routines to HIP and quantify currently achievable performance through the MAGMA benchmarks for the main workload algorithms on MI25 and MI50 AMD GPUs. Comparison with performance roofline models and theoretical expectations are used to identify current limitations and directions for future improvements.}, author = {Cade Brown and Ahmad Abdelfattah and Stanimire Tomov and Jack Dongarra} } @conference {1470, title = {Docker Container based PaaS Cloud Computing Comprehensive Benchmarks using LAPACK}, booktitle = {Computer Modeling and Intelligent Systems CMIS-2020}, year = {2020}, month = {2020-03}, address = {Zaporizhzhoa}, abstract = {Platform as a Service (PaaS) cloud computing model becomes wide- spread implemented within Docker Containers. Docker uses operating system level virtualization to deliver software in packages called containers. Containers are isolated from one another and comprise all the required software, including operating system API, libraries and configuration files. With such advantageous integrity one can doubt on Docker performance. The present paper applies packet LAPACK, which is widely used for performance benchmarks of super- computers, to collect and compare benchmarks of Docker on Linux Ubuntu and MS Windows platforms. After a brief overview of Docker and LAPACK, a se- ries of Docker images containing LAPACK is created and run, abundant benchmarks obtained and represented in tabular and graphical form. From the final discussion, we conclude that Docker runs with nearly the same perfor- mance on both Linux and Windows platforms, the slowdown does not exceed some ten percent. Though Docker performance in Windows is essentially lim- ited by the amount of RAM allocated to Docker Engine. }, keywords = {docker containers, software containers}, author = {Dmitry Zaitsev and Piotr Luszczek} } @article {, title = {DTE: PaRSEC Enabled Libraries and Applications (Poster)}, year = {2020}, month = {2020-02}, publisher = {2020 Exascale Computing Project Annual Meeting}, address = {Houston, TX}, author = {George Bosilca and Thomas Herault and Jack Dongarra} } @article {, title = {DTE: PaRSEC Systems and Interfaces (Poster)}, year = {2020}, month = {2020-02}, publisher = {2020 Exascale Computing Project Annual Meeting}, address = {Houston, TX}, author = {George Bosilca and Thomas Herault and Jack Dongarra} } @conference {1439, title = {Data Logistics: Toolkit and Applications}, booktitle = {5th EAI International Conference on Smart Objects and Technologies for Social Good}, year = {2019}, month = {2019-09}, address = {Valencia, Spain}, author = {Micah Beck and Terry Moore and Nancy French and Erza Kissel and Martin Swany} } @techreport {1322, title = {Design and Implementation for FFT-ECP on Distributed Accelerated Systems}, journal = {Innovative Computing Laboratory Technical Report}, number = {ICL-UT-19-05}, year = {2019}, month = {2019-04}, publisher = {University of Tennessee}, type = {ECP WBS 2.3.3.09 Milestone Report}, author = {Stanimire Tomov and Azzam Haidar and Alan Ayala and Daniel Schultz and Jack Dongarra} } @article {1370, title = {Distributed-Memory Lattice H-Matrix Factorization}, journal = { The International Journal of High Performance Computing Applications}, volume = {33}, year = {2019}, month = {2019-08}, pages = {1046{\textendash}1063}, abstract = {We parallelize the LU factorization of a hierarchical low-rank matrix (ℋ-matrix) on a distributed-memory computer. This is much more difficult than the ℋ-matrix-vector multiplication due to the dataflow of the factorization, and it is much harder than the parallelization of a dense matrix factorization due to the irregular hierarchical block structure of the matrix. Block low-rank (BLR) format gets rid of the hierarchy and simplifies the parallelization, often increasing concurrency. However, this comes at a price of losing the near-linear complexity of the ℋ-matrix factorization. In this work, we propose to factorize the matrix using a {\textquotedblleft}lattice ℋ-matrix{\textquotedblright} format that generalizes the BLR format by storing each of the blocks (both diagonals and off-diagonals) in the ℋ-matrix format. These blocks stored in the ℋ-matrix format are referred to as lattices. Thus, this lattice format aims to combine the parallel scalability of BLR factorization with the near-linear complexity of ℋ-matrix factorization. We first compare factorization performances using the ℋ-matrix, BLR, and lattice ℋ-matrix formats under various conditions on a shared-memory computer. Our performance results show that the lattice format has storage and computational complexities similar to those of the ℋ-matrix format, and hence a much lower cost of factorization than BLR. We then compare the BLR and lattice ℋ-matrix factorization on distributed-memory computers. Our performance results demonstrate that compared with BLR, the lattice format with the lower cost of factorization may lead to faster factorization on the distributed-memory computer.}, doi = {https://doi.org/10.1177/1094342019861139}, author = {Ichitaro Yamazaki and Akihiro Ida and Rio Yokota and Jack Dongarra} } @article {1387, title = {Does your tool support PAPI SDEs yet?}, year = {2019}, month = {2019-07}, publisher = {13th Scalable Tools Workshop}, address = {Tahoe City, CA}, author = {Anthony Danalis and Heike Jagode and Jack Dongarra} } @techreport {1200, title = {Data Movement Interfaces to Support Dataflow Runtimes}, journal = {Innovative Computing Laboratory Technical Report}, number = {ICL-UT-18-03}, year = {2018}, month = {2018-05}, publisher = {University of Tennessee}, abstract = {This document presents the design study and reports on the implementation of a portable hosted accelerator device support in the PaRSEC Dataflow Tasking at Exascale runtime, undertaken as part of the ECP contract 17-SC-20-SC. The document discusses different technological approaches to transfer data to/from hosted accelerators, issues recommendations for technology providers, and presents the design of an OpenMP-based accelerator support in PaRSEC.}, author = {Aurelien Bouteiller and George Bosilca and Thomas Herault and Jack Dongarra} } @inproceedings {1259, title = {The Design of Fast and Energy-Efficient Linear Solvers: On the Potential of Half-Precision Arithmetic and Iterative Refinement Techniques}, journal = {International Conference on Computational Science (ICCS 2018)}, volume = {10860}, year = {2018}, month = {2018-06}, pages = {586{\textendash}600}, publisher = {Springer}, address = {Wuxi, China}, abstract = {As parallel computers approach exascale, power efficiency in high-performance computing (HPC) systems is of increasing concern. Exploiting both the hardware features and algorithms is an effective solution to achieve power efficiency, and to address the energy constraints in modern and future HPC systems. In this work, we present a novel design and implementation of an energy-efficient solution for dense linear systems of equations, which are at the heart of large-scale HPC applications. The proposed energy-efficient linear system solvers are based on two main components: (1) iterative refinement techniques, and (2) reduced-precision computing features in modern accelerators and coprocessors. While most of the energy efficiency approaches aim to reduce the consumption with a minimal performance penalty, our method improves both the performance and the energy efficiency. Compared to highly-optimized linear system solvers, our kernels deliver the same accuracy solution up to 2{\texttimes} faster and reduce the energy consumption up to half on Intel Knights Landing (KNL) architectures. By efficiently using the Tensor Cores available in the NVIDIA V100 PCIe GPUs, the speedups can be up to 4{\texttimes} , with more than 80\% reduction in the energy consumption.}, doi = {https://doi.org/10.1007/978-3-319-93698-7_45}, url = {https://rdcu.be/bcKSC}, author = {Azzam Haidar and Ahmad Abdelfattah and Mawussi Zounon and Panruo Wu and Srikara Pranesh and Stanimire Tomov and Jack Dongarra} } @techreport {1320, title = {Distributed Termination Detection for HPC Task-Based Environments}, journal = {Innovative Computing Laboratory Technical Report}, number = {ICL-UT-18-14}, year = {2018}, month = {2018-06}, publisher = {University of Tennessee}, abstract = {This paper revisits distributed termination detection algorithms in the context of high-performance computing applications in task systems. We first outline the need to efficiently detect termination in workflows for which the total number of tasks is data dependent and therefore not known statically but only revealed dynamically during execution. We introduce an efficient variant of the Credit Distribution Algorithm (CDA) and compare it to the original algorithm (HCDA) as well as to its two primary competitors: the Four Counters algorithm (4C) and the Efficient Delay-Optimal Distributed algorithm (EDOD). On the theoretical side, we analyze the behavior of each algorithm for some simplified task-based kernels and show the superiority of CDA in terms of the number of control messages. On the practical side, we provide a highly tuned implementation of each termination detection algorithm within PaRSEC and compare their performance for a variety of benchmarks, extracted from scientific applications that exhibit dynamic behaviors.}, author = {George Bosilca and Aurelien Bouteiller and Thomas Herault and Valentin Le F{\`e}vre and Yves Robert and Jack Dongarra} } @conference {1214, title = {Do moldable applications perform better on failure-prone HPC platforms?}, booktitle = {11th Workshop on Resiliency in High Performance Computing in Clusters, Clouds, and Grids}, series = {LNCS}, year = {2018}, month = {2018-08}, publisher = {Springer Verlag}, organization = {Springer Verlag}, address = {Turin, Italy}, abstract = {This paper compares the performance of different approaches to tolerate failures using checkpoint/restart when executed on large-scale failure-prone platforms. We study (i) Rigid applications, which use a constant number of processors throughout execution; (ii) Moldable applications, which can use a different number of processors after each restart following a fail-stop error; and (iii) GridShaped applications, which are moldable applications restricted to use rectangular processor grids (such as many dense linear algebra kernels). For each application type, we compute the optimal number of failures to tolerate before relinquishing the current allocation and waiting until a new resource can be allocated, and we determine the optimal yield that can be achieved. We instantiate our performance model with a realistic applicative scenario and make it publicly available for further usage.}, author = {Valentin Le F{\`e}vre and George Bosilca and Aurelien Bouteiller and Thomas Herault and Atsushi Hori and Yves Robert and Jack Dongarra} } @techreport {1105, title = {Dataflow Programming Paradigms for Computational Chemistry Methods}, journal = {Innovative Computing Laboratory Technical Report}, number = {ICL-UT-17-01}, year = {2017}, month = {2017-05}, publisher = {University of Tennessee}, type = {PhD Dissertation (Computer Science)}, address = {Knoxville, TN}, abstract = {The transition to multicore and heterogeneous architectures has shaped the High Performance Computing (HPC) landscape over the past decades. With the increase in scale, complexity, and heterogeneity of modern HPC platforms, one of the grim challenges for traditional programming models is to sustain the expected performance at scale. By contrast, dataflow programming models have been growing in popularity as a means to deliver a good balance between performance and portability in the post-petascale era. This work introduces dataflow programming models for computational chemistry methods, and compares different dataflow executions in terms of programmability, resource utilization, and scalability. This effort is driven by computational chemistry applications, considering that they comprise one of the driving forces of HPC. In particular, many-body methods, such as Coupled Cluster methods (CC), which are the "gold standard" to compute energies in quantum chemistry, are of particular interest for the applied chemistry community. On that account, the latest development for CC methods is used as the primary vehicle for this research, but our effort is not limited to CC and can be applied across other application domains. Two programming paradigms for expressing CC methods into a dataflow form, in order to make them capable of utilizing task scheduling systems, are presented. Explicit dataflow, is the programming model where the dataflow is explicitly specified by the developer, is contrasted with implicit dataflow, where a task scheduling runtime derives the dataflow. An abstract model is derived to explore the limits of the different dataflow programming paradigms.}, url = {http://trace.tennessee.edu/utk_graddiss/4469/}, author = {Heike Jagode} } @article {1165, title = {Design and Implementation of the PULSAR Programming System for Large Scale Computing}, journal = {Supercomputing Frontiers and Innovations}, volume = {4}, year = {2017}, abstract = {The objective of the PULSAR project was to design a programming model suitable for large scale machines with complex memory hierarchies, and to deliver a prototype implementation of a runtime system supporting that model. PULSAR tackled the challenge by proposing a programming model based on systolic processing and virtualization. The PULSAR programming model is quite simple, with point-to-point channels as the main communication abstraction. The runtime implementation is very lightweight and fully distributed, and provides multithreading, message-passing and multi-GPU offload capabilities. Performance evaluation shows good scalability up to one thousand nodes with one thousand GPU accelerators.}, doi = {10.14529/jsfi170101}, url = {http://superfri.org/superfri/article/view/121/210}, author = {Jakub Kurzak and Piotr Luszczek and Ichitaro Yamazaki and Yves Robert and Jack Dongarra} } @conference {1168, title = {The Design and Performance of Batched BLAS on Modern High-Performance Computing Systems}, booktitle = {International Conference on Computational Science (ICCS 2017)}, year = {2017}, month = {2017-06}, publisher = {Elsevier}, organization = {Elsevier}, address = {Z{\"u}rich, Switzerland}, abstract = {A current trend in high-performance computing is to decompose a large linear algebra problem into batches containing thousands of smaller problems, that can be solved independently, before collating the results. To standardize the interface to these routines, the community is developing an extension to the BLAS standard (the batched BLAS), enabling users to perform thousands of small BLAS operations in parallel whilst making efficient use of their hardware. We discuss the benefits and drawbacks of the current batched BLAS proposals and perform a number of experiments, focusing on a general matrix-matrix multiplication (GEMM), to explore their affect on the performance. In particular we analyze the effect of novel data layouts which, for example, interleave the matrices in memory to aid vectorization and prefetching of data. Utilizing these modifications our code outperforms both MKL1 CuBLAS2 by up to 6 times on the self-hosted Intel KNL (codenamed Knights Landing) and Kepler GPU architectures, for large numbers of double precision GEMM operations using matrices of size 2 {\texttimes} 2 to 20 {\texttimes} 20.}, keywords = {Batched BLAS, BLAS, High-performance computing, Memory management, Parallel processing, Scientific computing}, doi = {DOI:10.1016/j.procs.2017.05.138}, author = {Jack Dongarra and Sven Hammarling and Nicholas J. Higham and Samuel Relton and Pedro Valero-Lara and Mawussi Zounon} } @techreport {1133, title = {Designing SLATE: Software for Linear Algebra Targeting Exascale}, journal = {SLATE Working Notes}, number = {03, ICL-UT-17-06}, year = {2017}, month = {2017-10}, publisher = {Innovative Computing Laboratory, University of Tennessee}, type = {SLATE Working Notes}, author = {Jakub Kurzak and Panruo Wu and Mark Gates and Ichitaro Yamazaki and Piotr Luszczek and Gerald Ragghianti and Jack Dongarra} } @inproceedings {1183, title = {Dynamic Task Discovery in PaRSEC- A data-flow task-based Runtime}, journal = {ScalA17}, year = {2017}, month = {2017-09}, publisher = {ACM}, address = {Denver}, abstract = {Successfully exploiting distributed collections of heterogeneous many-cores architectures with complex memory hierarchy through a portable programming model is a challenge for application developers. The literature is not short of proposals addressing this problem, including many evolutionary solutions that seek to extend the capabilities of current message passing paradigms with intranode features (MPI+X). A different, more revolutionary, solution explores data-flow task-based runtime systems as a substitute to both local and distributed data dependencies management. The solution explored in this paper, PaRSEC, is based on such a programming paradigm, supported by a highly efficient task-based runtime. This paper compares two programming paradigms present in PaRSEC, Parameterized Task Graph (PTG) and Dynamic Task Discovery (DTD) in terms of capabilities, overhead and potential benefits.}, keywords = {data-flow, dynamic task-graph, parsec, task-based runtime}, isbn = {978-1-4503-5125-6}, doi = {10.1145/3148226.3148233}, url = {https://dl.acm.org/citation.cfm?doid=3148226.3148233}, author = {Reazul Hoque and Thomas Herault and George Bosilca and Jack Dongarra} } @inbook {883, title = {Dense Symmetric Indefinite Factorization on GPU Accelerated Architectures}, booktitle = {Lecture Notes in Computer Science}, series = {11th International Conference, PPAM 2015, Krakow, Poland, September 6-9, 2015. Revised Selected Papers, Part I}, volume = {9573}, year = {2016}, month = {2015-09}, pages = {86-95}, publisher = {Springer International Publishing}, organization = {Springer International Publishing}, chapter = {Parallel Processing and Applied Mathematics}, abstract = {We study the performance of dense symmetric indefinite factorizations (Bunch-Kaufman and Aasen{\textquoteright}s algorithms) on multicore CPUs with a Graphics Processing Unit (GPU). Though such algorithms are needed in many scientific and engineering simulations, obtaining high performance of the factorization on the GPU is difficult because the pivoting that is required to ensure the numerical stability of the factorization leads to frequent synchronizations and irregular data accesses. As a result, until recently, there has not been any implementation of these algorithms on hybrid CPU/GPU architectures. To improve their performance on the hybrid architecture, we explore different techniques to reduce the expensive communication and synchronization between the CPU and GPU, or on the GPU. We also study the performance of an LDL^T factorization with no pivoting combined with the preprocessing technique based on Random Butterfly Transformations. Though such transformations only have probabilistic results on the numerical stability, they avoid the pivoting and obtain a great performance on the GPU. }, keywords = {Communication-avoiding, Dense symmetric indefinite factorization, gpu computation, randomization}, isbn = {978-3-319-32149-3}, doi = {10.1007/978-3-319-32149-3_9}, author = {Marc Baboulin and Jack Dongarra and Adrien Remy and Stanimire Tomov and Ichitaro Yamazaki}, editor = {Roman Wyrzykowski and Ewa Deelman and Konrad Karczewski and Jacek Kitowski and Kazimierz Wiatr} } @conference {940, title = {On the Development of Variable Size Batched Computation for Heterogeneous Parallel Architectures}, booktitle = {The 17th IEEE International Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC 2016), IPDPS 2016}, year = {2016}, month = {2016-05}, publisher = {IEEE}, organization = {IEEE}, address = {Chicago, IL}, abstract = {

Many scientific applications, ranging from national security to medical advances, require solving a number of relatively small-size independent problems. As the size of each individual problem does not provide sufficient parallelism for the underlying hardware, especially accelerators, these problems must be solved concurrently as a batch in order to saturate the hardware with enough work, hence the name batched computation. A possible simplification is to assume a uniform size for all problems. However, real applications do not necessarily satisfy such assumption. Consequently, an efficient solution for variable-size batched computations is required.

This paper proposes a foundation for high performance variable-size batched matrix computation based on Graphics Processing Units (GPUs). Being throughput-oriented processors, GPUs favor regular computation and less divergence among threads, in order to achieve high performance. Therefore, the development of high performance numerical software for this kind of problems is challenging. As a case study, we developed efficient batched Cholesky factorization algorithms for relatively small matrices of different sizes. However, most of the strategies and the software developed, and in particular a set of variable size batched BLAS kernels, can be used in many other dense matrix factorizations, large scale sparse direct multifrontal solvers, and applications. We propose new interfaces and mechanisms to handle the irregular computation pattern on the GPU. According to the authors{\textquoteright} knowledge, this is the first attempt to develop high performance software for this class of problems. Using a K40c GPU, our performance tests show speedups of up to 2:5 against two Sandy Bridge CPUs (8-core each) running Intel MKL library.

}, keywords = {batched computation, GPUs, variable small sizes}, author = {Ahmad Abdelfattah and Azzam Haidar and Stanimire Tomov and Jack Dongarra} } @inproceedings {996, title = {Domain Overlap for Iterative Sparse Triangular Solves on GPUs}, journal = {Software for Exascale Computing - SPPEXA}, volume = {113}, year = {2016}, month = {2016-09}, pages = {527{\textendash}545}, publisher = {Springer International Publishing}, abstract = {Iterative methods for solving sparse triangular systems are an attractive alternative to exact forward and backward substitution if an approximation of the solution is acceptable. On modern hardware, performance benefits are available as iterative methods allow for better parallelization. In this paper, we investigate how block-iterative triangular solves can benefit from using overlap. Because the matrices are triangular, we use {\textquotedblleft}directed{\textquotedblright} overlap, depending on whether the matrix is upper or lower triangular. We enhance a GPU implementation of the block-asynchronous Jacobi method with directed overlap. For GPUs and other cases where the problem must be overdecomposed, i.e., more subdomains and threads than cores, there is a preference in processing or scheduling the subdomains in a specific order, following the dependencies specified by the sparse triangular matrix. For sparse triangular factors from incomplete factorizations, we demonstrate that moderate directed overlap with subdomain scheduling can improve convergence and time-to-solution.}, doi = {10.1007/978-3-319-40528-5_24}, author = {Hartwig Anzt and Edmond Chow and Daniel Szyld and Jack Dongarra}, editor = {Hans-Joachim Bungartz and Philipp Neumann and Wolfgang E. Nagel} } @conference {842, title = { A Data Flow Divide and Conquer Algorithm for Multicore Architecture}, booktitle = {29th IEEE International Parallel \& Distributed Processing Symposium (IPDPS)}, year = {2015}, month = {2015-05}, publisher = {IEEE}, organization = {IEEE}, address = {Hyderabad, India}, abstract = {Computing eigenpairs of a symmetric matrix is a problem arising in many industrial applications, including quantum physics and finite-elements computation for automobiles. A classical approach is to reduce the matrix to tridiagonal form before computing eigenpairs of the tridiagonal matrix. Then, a back-transformation allows one to obtain the final solution. Parallelism issues of the reduction stage have already been tackled in different shared-memory libraries. In this article, we focus on solving the tridiagonal eigenproblem, and we describe a novel implementation of the Divide and Conquer algorithm. The algorithm is expressed as a sequential task-flow, scheduled in an out-of-order fashion by a dynamic runtime which allows the programmer to play with tasks granularity. The resulting implementation is between two and five times faster than the equivalent routine from the Intel MKL library, and outperforms the best MRRR implementation for many matrices.}, keywords = {Eigensolver, lapack, Multicore, plasma, task-based programming}, author = {Azzam Haidar and Jakub Kurzak and Gregoire Pichon and Mathieu Faverge} } @article {1345, title = {On the Design, Autotuning, and Optimization of GPU Kernels for Kinetic Network Simulations Using Fast Explicit Integration and GPU Batched Computation}, year = {2015}, month = {2015-09}, publisher = {Joint Institute for Computational Sciences Seminar Series, Presentation}, address = {Oak Ridge, TN}, author = {Michael Guidry and Azzam Haidar} } @conference {862, title = {On the Design, Development, and Analysis of Optimized Matrix-Vector Multiplication Routines for Coprocessors}, booktitle = {ISC High Performance 2015}, year = {2015}, month = {2015-07}, address = {Frankfurt, Germany}, abstract = {The dramatic change in computer architecture due to the manycore paradigm shift, made the development of numerical routines that are optimal extremely challenging. In this work, we target the development of numerical algorithms and implementations for Xeon Phi coprocessor architecture designs. In particular, we examine and optimize the general and symmetric matrix-vector multiplication routines (gemv/symv), which are some of the most heavily used linear algebra kernels in many important engineering and physics applications. We describe a successful approach on how to address the challenges for this problem, starting from our algorithm design, performance analysis and programing model, to kernel optimization. Our goal, by targeting low-level, easy to understand fundamental kernels, is to develop new optimization strategies that can be effective elsewhere for the use on manycore coprocessors, and to show significant performance improvements compared to the existing state-of-the-art implementations. Therefore, in addition to the new optimization strategies, analysis, and optimal performance results, we finally present the significance of using these routines/strategies to accelerate higher-level numerical algorithms for the eigenvalue problem (EVP) and the singular value decomposition (SVD) that by themselves are foundational for many important applications.}, author = {Khairul Kabir and Azzam Haidar and Stanimire Tomov and Jack Dongarra} } @conference {840, title = {Design for a Soft Error Resilient Dynamic Task-based Runtime}, booktitle = {29th IEEE International Parallel \& Distributed Processing Symposium (IPDPS)}, year = {2015}, month = {2015-05}, publisher = {IEEE}, organization = {IEEE}, address = {Hyderabad, India}, abstract = {As the scale of modern computing systems grows, failures will happen more frequently. On the way to Exascale a generic, low-overhead, resilient extension becomes a desired aptitude of any programming paradigm. In this paper we explore three additions to a dynamic task-based runtime to build a generic framework providing soft error resilience to task-based programming paradigms. The first recovers the application by re-executing the minimum required sub-DAG, the second takes critical checkpoints of the data flowing between tasks to minimize the necessary re-execution, while the last one takes advantage of algorithmic properties to recover the data without re-execution. These mechanisms have been implemented in the PaRSEC task-based runtime framework. Experimental results validate our approach and quantify the overhead introduced by such mechanisms.}, author = {Chongxiao Cao and George Bosilca and Thomas Herault and Jack Dongarra} } @conference {819, title = {Deflation Strategies to Improve the Convergence of Communication-Avoiding GMRES}, booktitle = {5th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems}, year = {2014}, month = {2014-11}, address = {New Orleans, LA}, author = {Ichitaro Yamazaki and Stanimire Tomov and Jack Dongarra} } @conference {710, title = {Design and Implementation of a Large Scale Tree-Based QR Decomposition Using a 3D Virtual Systolic Array and a Lightweight Runtime}, booktitle = {Workshop on Large-Scale Parallel Processing, IPDPS 2014}, year = {2014}, month = {2014-05}, publisher = {IEEE}, organization = {IEEE}, address = {Phoenix, AZ}, abstract = {A systolic array provides an alternative computing paradigm to the von Neuman architecture. Though its hardware implementation has failed as a paradigm to design integrated circuits in the past, we are now discovering that the systolic array as a software virtualization layer can lead to an extremely scalable execution paradigm. To demonstrate this scalability, in this paper, we design and implement a 3D virtual systolic array to compute a tile QR decomposition of a tall-and-skinny dense matrix. Our implementation is based on a state-of-the-art algorithm that factorizes a panel based on a tree-reduction. Using a runtime developed as a part of the Parallel Ultra Light Systolic Array Runtime (PULSAR) project, we demonstrate on a Cray-XT5 machine how our virtual systolic array can be mapped to a large-scale machine and obtain excellent parallel performance. This is an important contribution since such a QR decomposition is used, for example, to compute a least squares solution of an overdetermined system, which arises in many scientific and engineering problems.}, keywords = {dataflow, message-passing, multithreading, QR decomposition, runtime, systolic array}, author = {Ichitaro Yamazaki and Jakub Kurzak and Piotr Luszczek and Jack Dongarra} } @techreport {822, title = {Design for a Soft Error Resilient Dynamic Task-based Runtime}, journal = {ICL Technical Report}, number = {ICL-UT-14-04}, year = {2014}, month = {2014-11}, publisher = {University of Tennessee}, abstract = {Abstract{\textemdash}As the scale of modern computing systems grows, failures will happen more frequently. On the way to Exascale a generic, low-overhead, resilient extension becomes a desired aptitude of any programming paradigm. In this paper we explore three additions to a dynamic task-based runtime to build a generic framework providing soft error resilience to task-based programming paradigms. The first recovers the application by re-executing the minimum required sub-DAG, the second takes critical checkpoints of the data flowing between tasks to minimize the necessary re-execution, while the last one takes advantage of algorithmic properties to recover the data without re-execution. These mechanisms have been implemented in the PaRSEC task-based runtime framework. Experimental results validate our approach and quantify the overhead introduced by such mechanisms.}, author = {Chongxiao Cao and Thomas Herault and George Bosilca and Jack Dongarra} } @conference {813, title = {Designing LU-QR Hybrid Solvers for Performance and Stability}, booktitle = {IPDPS 2014}, year = {2014}, month = {2014-05}, publisher = {IEEE}, organization = {IEEE}, address = {Phoenix, AZ}, abstract = {This paper introduces hybrid LU-QR algorithms for solving dense linear systems of the form Ax = b. Throughout a matrix factorization, these algorithms dynamically alternate LU with local pivoting and QR elimination steps, based upon some robustness criterion. LU elimination steps can be very efficiently parallelized, and are twice as cheap in terms of operations, as QR steps. However, LU steps are not necessarily stable, while QR steps are always stable. The hybrid algorithms execute a QR step when a robustness criterion detects some risk for instability, and they execute an LU step otherwise. Ideally, the choice between LU and QR steps must have a small computational overhead and must provide a satisfactory level of stability with as few QR steps as possible. In this paper, we introduce several robustness criteria and we establish upper bounds on the growth factor of the norm of the updated matrix incurred by each of these criteria. In addition, we describe the implementation of the hybrid algorithms through an extension of the Parsec software to allow for dynamic choices during execution. Finally, we analyze both stability and performance results compared to state-of-the-art linear solvers on parallel distributed multicore platforms.}, keywords = {plasma}, isbn = {978-1-4799-3800-1}, doi = {10.1109/IPDPS.2014.108}, author = {Mathieu Faverge and Julien Herrmann and Julien Langou and Bradley Lowery and Yves Robert and Jack Dongarra} } @conference {816, title = {Domain Decomposition Preconditioners for Communication-Avoiding Krylov Methods on a Hybrid CPU/GPU Cluster}, booktitle = {The International Conference for High Performance Computing, Networking, Storage and Analysis (SC 14)}, year = {2014}, month = {2014-11}, publisher = {IEEE}, organization = {IEEE}, address = {New Orleans, LA}, author = {Ichitaro Yamazaki and Sivasankaran Rajamanickam and Eric G. Boman and Mark Hoemmen and Michael A. Heroux and Stanimire Tomov} } @conference {834, title = {Dynamically balanced synchronization-avoiding LU factorization with multicore and GPUs}, booktitle = {Fourth International Workshop on Accelerators and Hybrid Exascale Systems (AsHES), IPDPS 2014}, year = {2014}, month = {2014-05}, abstract = {Graphics processing units (GPUs) brought huge performance improvements in the scientific and numerical fields. We present an efficient hybrid CPU/GPU approach that is portable, dynamically and efficiently balances the workload between the CPUs and the GPUs, and avoids data transfer bottlenecks that are frequently present in numerical algorithms. Our approach determines the amount of initial work to assign to the CPUs before the execution, and then dynamically balances workloads during the execution. Then, we present a theoretical model to guide the choice of the initial amount of work for the CPUs. The validation of our model allows our approach to self-adapt on any architecture using the manufacturer{\textquoteright}s characteristics of the underlying machine. We illustrate our method for the LU factorization. For this case, we show that the use of our approach combined with a communication avoiding LU algorithm is efficient. For example, our experiments on a 24 cores AMD Opteron 6172 show that by adding one GPU (Tesla S2050) we accelerate LU up to 2.4x compared to the corresponding routine in MKL using 24 cores. The comparisons with MAGMA also show significant improvements.}, author = {Simplice Donfack and Stanimire Tomov and Jack Dongarra} } @article {icl:698, title = {Dense Linear Algebra on Distributed Heterogeneous Hardware with a Symbolic DAG Approach}, journal = {Scalable Computing and Communications: Theory and Practice}, year = {2013}, month = {2013-03}, pages = {699-735}, publisher = {John Wiley \& Sons}, author = {George Bosilca and Aurelien Bouteiller and Anthony Danalis and Thomas Herault and Piotr Luszczek and Jack Dongarra}, editor = {Samee Khan and Lin-Wang Wang and Albert Zomaya} } @techreport {703, title = {Designing LU-QR hybrid solvers for performance and stability}, journal = {University of Tennessee Computer Science Technical Report (also LAWN 282)}, number = {ut-eecs-13-719}, year = {2013}, month = {2013-10}, publisher = {University of Tennessee}, author = {Mathieu Faverge and Julien Herrmann and Julien Langou and Bradley Lowery and Yves Robert and Jack Dongarra} } @conference {687, title = {Diagnosis and Optimization of Application Prefetching Performance}, booktitle = {Proceedings of the 27th ACM International Conference on Supercomputing (ICS {\textquoteright}13)}, year = {2013}, month = {2013-06}, publisher = {ACM Press}, organization = {ACM Press}, address = {Eugene, Oregon, USA}, abstract = {Hardware prefetchers are effective at recognizing streaming memory access patterns and at moving data closer to the processing units to hide memory latency. However, hardware prefetchers can track only a limited number of data streams due to finite hardware resources. In this paper, we introduce the term streaming concurrency to characterize the number of parallel, logical data streams in an application. We present a simulation algorithm for understanding the streaming concurrency at any point in an application, and we show that this metric is a good predictor of the number of memory requests initiated by streaming prefetchers. Next, we try to understand the causes behind poor prefetching performance. We identified four prefetch unfriendly conditions and we show how to classify an application{\textquoteright}s memory references based on these conditions. We evaluated our analysis using the SPEC CPU2006 benchmark suite. We selected two benchmarks with unfavorable access patterns and transformed them to improve their prefetching effectiveness. Results show that making applications more prefetcher friendly can yield meaningful performance gains.}, isbn = {9781450321303}, doi = {10.1145/2464996.2465014}, url = {http://dl.acm.org/citation.cfm?doid=2464996.2465014}, author = {Gabriel Marin and Colin McCurdy and Jeffrey Vetter}, editor = {Allen D. Malony and Nemirovsky, Mario and Midkiff, Sam} } @techreport {689, title = {Dynamically balanced synchronization-avoiding LU factorization with multicore and GPUs}, journal = {University of Tennessee Computer Science Technical Report}, number = {ut-cs-13-713}, year = {2013}, month = {2013-07}, abstract = {Graphics processing units (GPUs) brought huge performance improvements in the scientific and numerical fields. We present an efficient hybrid CPU/GPU computing approach that is portable, dynamically and efficiently balances the workload between the CPUs and the GPUs, and avoids data transfer bottlenecks that are frequently present in numerical algorithms. Our approach determines the amount of initial work to assign to the CPUs before the execution, and then dynamically balances workloads during the execution. Then, we present a theoretical model to guide the choice of the initial amount of work for the CPUs. The validation of our model allows our approach to self-adapt on any architecture using the manufacturer{\textquoteright}s characteristics of the underlying machine. We illustrate our method for the LU factorization. For this case, we show that the use of our approach combined with a communication avoiding LU algorithm is efficient. For example, our experiments on high-end hybrid CPU/GPU systems show that our dynamically balanced synchronization-avoiding LU is both multicore and GPU scalable. Comparisons with state-of-the-art libraries like MKL (for multicore) and MAGMA (for hybrid systems) are provided, demonstrating significant performance improvements. The approach is applicable to other linear algebra algorithms. The scheduling mechanisms and tuning models can be incorporated into respectively dynamic runtime systems/schedulers and autotuning frameworks for hybrid CPU/MIC/GPU architectures.}, author = {Simplice Donfack and Stanimire Tomov and Jack Dongarra} } @article {icl:670, title = {DAGuE: A generic distributed DAG Engine for High Performance Computing.}, journal = {Parallel Computing}, volume = {38}, number = {1-2}, year = {2012}, month = {2012-00}, pages = {27-51}, publisher = {Elsevier}, keywords = {dague, parsec}, author = {George Bosilca and Aurelien Bouteiller and Anthony Danalis and Thomas Herault and Pierre Lemariner and Jack Dongarra} } @article {icl:703, title = {Dense Linear Algebra on Accelerated Multicore Hardware}, journal = {High Performance Scientific Computing: Algorithms and Applications}, year = {2012}, month = {2012-00}, publisher = {Springer-Verlag}, address = {London, UK}, author = {Jack Dongarra and Jakub Kurzak and Piotr Luszczek and Stanimire Tomov}, editor = {Michael Berry and et al.,} } @article {icl:684, title = {Divide and Conquer on Hybrid GPU-Accelerated Multicore Systems}, journal = {SIAM Journal on Scientific Computing}, volume = {34(2)}, year = {2012}, month = {2012-04}, pages = {C70-C82}, keywords = {magma}, author = {Christof Voemel and Stanimire Tomov and Jack Dongarra} } @article {697, title = {Dynamic Task Execution on Shared and Distributed Memory Architectures}, year = {2012}, type = {Dissertation}, abstract = {Multicore architectures with high core counts have come to dominate the world of high performance computing, from shared memory machines to the largest distributed memory clusters. The multicore route to increased performance has a simpler design and better power efficiency than the traditional approach of increasing processor frequencies. But, standard programming techniques are not well adapted to this change in computer architecture design. In this work, we study the use of dynamic runtime environments executing data driven applications as a solution to programming multicore architectures. The goals of our runtime environments are productivity, scalability and performance. We demonstrate productivity by defining a simple programming interface to express code. Our runtime environments are experimentally shown to be scalable and give competitive performance on large multicore and distributed memory machines. This work is driven by linear algebra algorithms, where state-of-the-art libraries (e.g., LAPACK and ScaLAPACK) using a fork-join or block-synchronous execution style do not use the available resources in the most efficient manner. Research work in linear algebra has reformulated these algorithms as tasks acting on tiles of data, with data dependency relationships between the tasks. This results in a task-based DAG for the reformulated algorithms, which can be executed via asynchronous data-driven execution paths analogous to dataflow execution. We study an API and runtime environment for shared memory architectures that efficiently executes serially presented tile based algorithms. This runtime is used to enable linear algebra applications and is shown to deliver performance competitive with state-ofthe-art commercial and research libraries. We develop a runtime environment for distributed memory multicore architectures extended from our shared memory implementation. The runtime takes serially presented algorithms designed for the shared memory environment, and schedules and executes them on distributed memory architectures in a scalable and high performance manner. We design a distributed data coherency protocol and a distributed task scheduling mechanism which avoid global coordination. Experimental results with linear algebra applications show the scalability and performance of our runtime environment.}, author = {Asim YarKhan} } @inproceedings {icl:675, title = {DAGuE: A Generic Distributed DAG Engine for High Performance Computing}, journal = {Proceedings of the Workshops of the 25th IEEE International Symposium on Parallel and Distributed Processing (IPDPS 2011 Workshops)}, year = {2011}, month = {2011-00}, pages = {1151-1158}, publisher = {IEEE}, address = {Anchorage, Alaska, USA}, keywords = {dague, parsec}, author = {George Bosilca and Aurelien Bouteiller and Anthony Danalis and Thomas Herault and Pierre Lemariner and Jack Dongarra} } @inproceedings {icl:615, title = {The Design of an Auto-tuning I/O Framework on Cray XT5 System}, journal = {Cray Users Group Conference (CUG{\textquoteright}11) (Best Paper Finalist)}, year = {2011}, month = {2011-05}, address = {Fairbanks, Alaska}, keywords = {gco}, author = {Haihang You and Qing Liu and Zhiqiang Li and Shirley Moore} } @techreport {icl:528, title = {DAGuE: A generic distributed DAG engine for high performance computing}, journal = {Innovative Computing Laboratory Technical Report}, number = {ICL-UT-10-01}, year = {2010}, month = {2010-04}, keywords = {dague}, author = {George Bosilca and Aurelien Bouteiller and Anthony Danalis and Thomas Herault and Pierre Lemariner and Jack Dongarra} } @inbook {855, title = {Dense Linear Algebra for Hybrid GPU-based Systems}, booktitle = {Scientific Computing with Multicore and Accelerators}, series = {Chapman \& Hall/CRC Computational Science}, year = {2010}, publisher = {CRC Press}, organization = {CRC Press}, chapter = {3}, address = {Boca Raton, Florida}, isbn = {9781439825365}, author = {Stanimire Tomov and Jack Dongarra} } @article {1351, title = {Dense Linear Algebra Solvers for Multicore with GPU Accelerators}, year = {2010}, month = {2010-04}, publisher = {International Parallel and Distributed Processing Symposium (IPDPS 2010)}, address = {Atlanta, GA}, author = {Stanimire Tomov} } @inproceedings {icl:523, title = {Dense Linear Algebra Solvers for Multicore with GPU Accelerators}, journal = {Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on}, year = {2010}, pages = {1-8}, address = {Atlanta, GA}, abstract = {Solving dense linear systems of equations is a fundamental problem in scientific computing. Numerical simulations involving complex systems represented in terms of unknown variables and relations between them often lead to linear systems of equations that must be solved as fast as possible. We describe current efforts toward the development of these critical solvers in the area of dense linear algebra (DLA) for multicore with GPU accelerators. We describe how to code/develop solvers to effectively use the high computing power available in these new and emerging hybrid architectures. The approach taken is based on hybridization techniques in the context of Cholesky, LU, and QR factorizations. We use a high-level parallel programming model and leverage existing software infrastructure, e.g. optimized BLAS for CPU and GPU, and LAPACK for sequential CPU processing. Included also are architecture and algorithm-specific optimizations for standard solvers as well as mixed-precision iterative refinement solvers. The new algorithms, depending on the hardware configuration and routine parameters, can lead to orders of magnitude acceleration when compared to the same algorithms on standard multicore architectures that do not contain GPU accelerators. The newly developed DLA solvers are integrated and freely available through the MAGMA library.}, doi = {10.1109/IPDPSW.2010.5470941}, author = {Stanimire Tomov and Rajib Nath and Hatem Ltaeif and Jack Dongarra} } @techreport {icl:563, title = {Distributed Dense Numerical Linear Algebra Algorithms on Massively Parallel Architectures: DPLASMA}, journal = {University of Tennessee Computer Science Technical Report, UT-CS-10-660}, year = {2010}, month = {2010-09}, keywords = {dague, dplasma, parsec, plasma}, author = {George Bosilca and Aurelien Bouteiller and Anthony Danalis and Mathieu Faverge and Azzam Haidar and Thomas Herault and Jakub Kurzak and Julien Langou and Pierre Lemariner and Hatem Ltaeif and Piotr Luszczek and Asim YarKhan and Jack Dongarra} } @techreport {icl:529, title = {Distributed-Memory Task Execution and Dependence Tracking within DAGuE and the DPLASMA Project}, journal = {Innovative Computing Laboratory Technical Report}, number = {ICL-UT-10-02}, year = {2010}, month = {2010-00}, keywords = {dague, plasma}, author = {George Bosilca and Aurelien Bouteiller and Anthony Danalis and Mathieu Faverge and Azzam Haidar and Thomas Herault and Jakub Kurzak and Julien Langou and Pierre Lemariner and Hatem Ltaeif and Piotr Luszczek and Asim YarKhan and Jack Dongarra} } @article {icl:639, title = {Divide \& Conquer on Hybrid GPU-Accelerated Multicore Systems}, journal = {SIAM Journal on Scientific Computing (submitted)}, year = {2010}, month = {2010-08}, keywords = {magma}, author = {Christof Voemel and Stanimire Tomov and Jack Dongarra} } @inproceedings {icl:534, title = {Dodging the Cost of Unavoidable Memory Copies in Message Logging Protocols}, journal = {Proceedings of EuroMPI 2010}, year = {2010}, month = {2010-09}, publisher = {Springer}, address = {Stuttgart, Germany}, keywords = {ftmpi}, author = {George Bosilca and Aurelien Bouteiller and Thomas Herault and Pierre Lemariner and Jack Dongarra}, editor = {Jack Dongarra and Michael Resch and Rainer Keller and Edgar Gabriel} } @article {icl:518, title = {Dependency-Driven Scheduling of Dense Matrix Factorizations on Shared-Memory Systems}, journal = {PPAM 2009}, year = {2009}, month = {2009-09}, address = {Poland}, author = {Jakub Kurzak and Hatem Ltaeif and Jack Dongarra and Rosa M. Badia} } @inproceedings {icl:493, title = {Dynamic Task Scheduling for Linear Algebra Algorithms on Distributed-Memory Multicore Systems}, journal = {International Conference for High Performance Computing, Networking, Storage, and Analysis (SC {\textquoteright}09)}, year = {2009}, month = {2009-11}, address = {Portland, OR}, keywords = {mumi, plasma}, author = {Fengguang Song and Asim YarKhan and Jack Dongarra} } @article {icl:451, title = {DARPA{\textquoteright}s HPCS Program: History, Models, Tools, Languages}, journal = {in Advances in Computers}, volume = {72}, year = {2008}, month = {2008-01}, publisher = {Elsevier}, author = {Jack Dongarra and Robert Graybill and William Harrod and Robert Lucas and Ewing Lusk and Piotr Luszczek and Janice McMahon and Allan Snavely and Jeffrey Vetter and Katherine Yelick and Sadaf Alam and Roy Campbell and Laura Carrington and Tzu-Yi Chen and Omid Khalili and Jeremy Meredith and Mustafa Tikir}, editor = {M. Zelkowitz} } @inproceedings {icl:429, title = {Detection and Analysis of Iterative Behavior in Parallel Applications}, journal = {Proceedings of the 2008 International Conference on Computational Science (ICCS 2008)}, volume = {5103}, year = {2008}, month = {2008-01}, pages = {261-267}, address = {Krakow, Poland}, keywords = {point}, author = {Karl F{\"u}rlinger and Shirley Moore} } @article {icl:357, title = {Decision Trees and MPI Collective Algorithm Selection Problem}, journal = {Euro-Par 2007}, year = {2007}, month = {2007-08}, pages = {105{\textendash}115}, publisher = {Springer}, address = {Rennes, France}, keywords = {ftmpi}, author = {Jelena Pjesivac{\textendash}Grbovic and George Bosilca and Graham Fagg and Thara Angskun and Jack Dongarra} } @article {icl:366, title = {Disaster Survival Guide in Petascale Computing: An Algorithmic Approach}, journal = {in Petascale Computing: Algorithms and Applications (to appear)}, year = {2007}, month = {2007-00}, publisher = {Chapman \& Hall - CRC Press}, author = {Jack Dongarra and Zizhong Chen and George Bosilca and Julien Langou} } @inproceedings {icl:293, title = {Dynamic Process Management for Pipelined Applications}, journal = {Proceedings of DoD HPCMP UGC 2005 (to appear)}, year = {2005}, month = {2005-01}, publisher = {IEEE}, address = {Nashville, TN}, author = {David Cronk and Graham Fagg and Susan Emeny and Scott Tucker} } @inproceedings {icl:201, title = {Design of an Interactive Environment for Numerically Intensive Parallel Linear Algebra Calculations}, journal = {International Conference on Computational Science}, year = {2004}, month = {2004-06}, publisher = {Springer Verlag}, address = {Poland}, keywords = {lacsi, lfc}, doi = {10.1007/978-3-540-25944-2_35}, author = {Piotr Luszczek and Jack Dongarra}, editor = {Marian Bubak and Geert Dick van Albada and Peter M. Sloot and Jack Dongarra} } @article {icl:175, title = {Distributed Probablistic Model-Building Genetic Algorithm}, journal = {Lecture Notes in Computer Science}, volume = {2723}, year = {2003}, month = {2003-01}, pages = {1015-1028}, publisher = {Springer-Verlag, Heidelberg}, author = {Tomoyuki Hiroyasu and Mitsunori Miki and Masaki Sano and Hisashi Shimosaka and Shigeyoshi Tsutsui and Jack Dongarra} } @article {icl:140, title = {Distributed Storage in RIB}, journal = {ICL Tech Report}, number = {ICL-UT-03-01}, year = {2003}, month = {2003-03}, keywords = {rib}, author = {Thomas B. Boehmann} } @inproceedings {icl:93, title = {Deploying Parallel Numerical Library Routines to Cluster Computing in a Self Adapting Fashion}, journal = {Parallel Computing: Advances and Current Issues:Proceedings of the International Conference ParCo2001}, year = {2002}, month = {2002-01}, publisher = {Imperial College Press}, address = {London, England}, keywords = {lfc, sans}, author = {Kenneth Roche and Jack Dongarra}, editor = {Gerhard R. Joubert and Almerica Murli and Frans Peters and Marco Vanneschi} } @techreport {icl:91, title = {Development of the PICMSS NetSolve Service}, journal = {ICL Technical Report}, number = {ICL-UT-02-04}, year = {2002}, month = {2002-04}, keywords = {netsolve}, author = {Matthew Kelleher Jr.} } @techreport {icl:47, title = {Design and Implementation of NetSolve using DCOM as the Remoting Layer}, journal = {University of Tennessee Computer Science Department Technical Report}, number = {UT-CS-00-440}, year = {2000}, month = {2000-05}, keywords = {netsolve}, author = {Ganapathy Raman and Jack Dongarra} } @article {icl:35, title = {The Design and Implementation of the Parallel Out of Core ScaLAPACK LU, QR, and Cholesky Factorization Routines}, journal = {Concurrency: Practice and Experience}, volume = {12}, number = {15}, year = {2000}, month = {2000-01}, pages = {1481-1493}, author = {Eduardo D{\textquoteright}Azevedo and Jack Dongarra} } @inproceedings {icl:27, title = {Developing an Architecture to Support the Implementation and Development of Scientific Computing Applications}, journal = {to appear in Proceedings of Working Conference 8: Software Architecture for Scientific Computing Applications}, year = {2000}, month = {2000-10}, address = {Ottawa, Canada}, keywords = {netsolve}, author = {Dorian Arnold and Jack Dongarra} } @article {icl:33, title = {Deploying Fault-tolerance and Task Migration with NetSolve}, journal = {Future Generation Computer Systems}, volume = {15}, number = {5-6}, year = {1999}, month = {1999-10}, pages = {745-755}, publisher = {Elsevier}, keywords = {netsolve}, author = {Henri Casanova and James Plank and Micah Beck and Jack Dongarra} }